Field of the Invention
This disclosure relates to generating clock signals and more particularly generating clock signals in a PLL with different power and jitter settings.
Description of the Related Art
Continuous-time delta-sigma modulator based analog to digital converters (ADCs) are widely used in radio frequency (RF) receiver (RX) applications. Typically, either higher-order delta-sigma modulator-based ADCs that use the reference clock (e.g., a crystal oscillator) or less complicated lower-order delta-sigma ADCs with high clock rates are employed. For the second case, in one solution clocks for the ADC are generated from divided down local oscillator (LO) clocks. However, the LO clock signal can change based on the tuned channel resulting in the ADC sampling frequency changing, thereby complicating modem design. Another approach uses a phase-locked loop (PLL) circuit as a clock multiplier unit for the ADC. Typically, these PLLs are not optimized for the delta-sigma ADCs and therefore consume high power and occupy large die area, increasing cost.
SUMMARY OF EMBODIMENTS OF THE INVENTION
A phase-locked loop (PLL) can be used to independently provide a fixed rate clock for the ADC in the RX signal chain, thereby simplifying modem design. In addition, it would be beneficial to reduce power consumed in the dedicated PLL.
In one embodiment, a phase-locked loop (PLL) includes a charge pump that provides a charge based on a difference between a reference signal and a feedback signal supplied by a phase and frequency detector. An active loop filter is coupled to an output node of the charge pump. A unity gain buffer is coupled to be used in the charge pump and in the active loop filter.
In another embodiment, a method for operating a phase-locked loop (PLL) includes generating signals indicating a difference between a reference signal and a feedback signal in a phase and frequency detector and supplying the signals indicating the difference to a charge pump. The method further includes using a unity gain buffer in the charge pump and using the unity gain buffer in an active loop filter and generating a filtered oscillator control signal using the charge pump and the active loop filter.
In another embodiment a PLL includes a phase and frequency detector (PFD) to provide PFD signals indicative of a difference between a reference signal and a feedback signal. A charge pump supplies a current to an output node of the charge pump based on the PFD signals. An active loop filter is coupled to the output node of the charge pump, the active loop filter providing an increased effective capacitance of a capacitor in the active loop filter. A unity gain buffer is coupled as part of the charge pump to reduce mismatch in the charge pump and the unity gain buffer is further coupled as part of the active loop filter. The charge pump includes a first transistor coupled between a first current source and the output node of the charge pump. A second transistor is coupled between a second current source and the output node of the charge pump. A third transistor is coupled between the first current source and a fourth transistor. The fourth transistor is coupled between the third transistor and the second current source. A positive input terminal of the unity gain buffer is coupled to the output node of the charge pump through a first resistor of the active loop filter. A second resistor of the active loop filter is coupled between the output node of the charge pump and an output terminal of the unity gain buffer. The capacitor of the active loop filter is coupled between the positive input terminal of the unity gain buffer and ground.
The use of the same reference symbols in different drawings indicates similar or identical items.